1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a high-frequency interconnect and dummy conductor patterns.
2. Description of the Related Art
FIGS. 7 and 8 are plan views each showing a semiconductor device according to a related art. In a semiconductor device 100, dummy conductor patterns 102 and 103 are disposed near a high-frequency interconnect 101. FIG. 7 shows a layer in which the high-frequency interconnect 101 is formed, and FIG. 8 shows another layer. In FIG. 8, a region overlapping the high-frequency interconnect 101 in a plan view is indicated by the dotted line.
The dummy conductor patterns 102 are disposed in the same layer as that of the high-frequency interconnect 101, and the dummy conductor patterns 103 are disposed in a layer different from the layer in which the high-frequency interconnect 101 is disposed. The dummy conductor patterns are disposed for the purpose of preventing a dishing, which is called erosion, from being easily generated in a region, in which a interconnect pattern density is low, during a chemical mechanical polishing (CMP) process. In other words, when the dummy conductor patterns 102 are disposed, a layer containing the high-frequency interconnect 101 is easily processed at the time of production of the semiconductor device 100. The dummy conductor patterns 103 are also disposed for the same reason. Further, the high-frequency interconnect 101 functions as an inductor.
The related arts of the present invention are disclosed in JP 2005-285970 A and Ali Hajimiri et al., “Design Issues in CMOS Differential LC Oscillators”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 34, No. 5, May 1999, pp. 717-724.
However, in the semiconductor device 100, in a case where a high-frequency current flows through the high-frequency interconnect 101, the following problem arises. That is, as shown in FIG. 9, due to a magnetic field generated by the high-frequency interconnect 101, an eddy current is generated in the dummy conductor patterns 102 which are positioned near the high-frequency interconnect 101. FIG. 9 is an enlarged plan view showing a portion surrounded by the dotted line of FIG. 7. In FIG. 9, an arrow A1 indicates a direction of the current flowing through the high-frequency interconnect 101, and an arrow A2 indicates a direction of the eddy current flowing through each of the dummy conductor patterns 102.
When the eddy current is generated as described above, according to Lenz's law, a magnetic field is generated in a direction in which the above-mentioned magnetic field is offset. Accordingly, a circuit constant of the high-frequency interconnect 101 fluctuates, which results in a change in transmission characteristics of the high-frequency interconnect 101.
The eddy current generated due to an effect of the magnetic field of the high-frequency interconnect 101 is generated not only in each of the dummy conductor patterns 102 disposed in the same layer as that of the high-frequency interconnect 101, but also in each of the dummy conductor patterns 103 disposed in another layer different from the layer in which the high-frequency interconnect 101 is disposed. The dummy conductor patterns 103 which are positioned closest to the high-frequency interconnect 101, that is, the dummy conductor patterns 103 (indicated by oblique lines of FIG. 8) which are positioned immediately above or immediately below the high-frequency interconnect are most significantly affected by the magnetic field of the high-frequency interconnect 101 in the different layer.